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GM Interface Introduction

The universal interface is designed to integrate memory controllers and distributed shared memory. "From Tukwila - 1 Itanium processor and Nehalem-1, an enhanced derivative processor with kernel microarchitecture launched in 2008 - the generic system interface is expected to be used in almost every future Intel system structure."

Overview of Common System Interfaces


In 2008 and 2009, Intel is expected to launch a new system for its microprocessors

System Architecture (Intel Architecture) - Common System Interface (CSI).

The Common System Interface (CSI) is a family interconnection interface that revolutionizes Intel's entire high-performance product, which replaces the existing front-side bus and is comparable to AMD's HyperTransport.

The Universal System Interface (CSI) is designed to integrate memory controllers and distributed shared memory. "From Tukwila - 1 Itanium processor and Nehalem-1, an enhanced derivative processor with kernel microarchitecture launched in 2008, the Common System Interface (CSI) is expected to be used in almost any future Intel The internal structure of the system. "[1]

Core i7 (Core i7) series processor mainly by the Core (processor core) and Uncore (processor core), Core includes four processor core and L1, L2 cache, Uncore including QPI bus controller, memory control And L3 cache. In order to distinguish between the market, Core i7 920 and Core i7 940 QPI bus has been reduced to 4.8GT / s, while the Core i7 Extreme Edition 965 was 6.4GT / s.

As the successor of Core architecture, Nehalem can be said to be standing on the shoulders of the giant. Both adhering to the Core Duo structure of the efficient assembly line design and mature process experience, but also on this basis to improve the lack of Core, and made more breakthroughs. Nehalem's performance leap will increase more than the year's Core, and some of its revolutionary milestones will affect or even lead the future of multi-core processors.

One of the biggest improvements in the Nehalem architecture is the abandonment of the traditional parallel transmission of the FSB front-side bus, instead of the Common System Interface (CSI) based on PCI Express serial point-to-point transmission technology, which is called the Quick Path interconnection system architecture called by intel. Quick Path includes integrated memory controller technology and improved communication links between system components, similar to AMD's Inter connect and Crossbar design, and in multi-processor operations, each processor can send data to each other, without going through Chipset, which greatly enhance the overall system performance.

Although the integrated memory controller can improve system performance, but this will also bring the cost increase and the processor frequency to enhance the problem. But in Nehalem, it is surprising to see its integrated DDR3 memory controller, according to intel said, Nehalem memory bandwidth can be increased up to 3 times!

QuickPath code

QuickPath previously announced code is the Common System Interface (CSI), its most important feature is the expansion of shared memory deployment. The way to do this is to use a single memory shared pool, through the FSB and memory controller hub connected to the server or high-end workstations in all the processors. In contrast, each processor in the QuickPath architecture has dedicated memory that is accessed directly through the processor's integrated memory controller. If a processor needs to access dedicated memory on another processor, it can be accessed through a high-speed QuickPath interconnect to all processors. With point-to-point interconnect mode, processors do not have to compete with each other for access to memory and I / O, thus increasing scalability.

The throughput of the QuickPath interconnects reflects its value in the server / workstation market, and the QuickPath interconnect uses up to 6.4GT / s of links, providing a total bandwidth of up to 25GB / s, and other interconnect solutions 3 Times The QuickPath interconnect reduces the amount of traffic required for a multipath system interface, accelerates the payload transmission speed, and exhibits RAS features such as reliability, availability, and maintainability.

Nehalem most of the microarchitecture design is still along the Yorkfield and Wolfdale, and has a native quad-core design. One of the most noteworthy innovations is its Quickpath structure. The new generation of Nehalem will give up the FSB design, using the new Quick Path Interconnect architecture, Nehalem is Intel's first use of the Quickpath interconnect system architecture processor products.

QuickPath has two major components. The first part is the built-in group component of the memory controller. The integrated memory controller can shorten the data transmission between the processor and the main memory. The second part is the direct connection technology between the processors, so that the chip can share the data, and In multiprocessor operations, each processor can send data to each other, without going through the chipset, which greatly enhance the overall system performance. Intel's two major chip series - mainstream x86, high-end server Itanium will use QuickPath technology.

To abandon the use of FSB design, use Quick Path Interconnect technology, two-way series point-to-point transmission. QuickPath is the highest speed of 6.4GT / s, the transmission rate is FSB 1333MHz 5 times, two-way maximum speed of a total of 10.8GT / s, than AMD used Hyper-Transport 3.0 higher speed.

Nehalem microarchitecture supports up to four processors in the Quick Path multi-socket server environment and can consist of at least four processors with data that can be interchangeably connected to a 4Ways server architecture. A single chip can have a maximum of 2,4 and 8 core, support for improved Hyper-Theading technology, so that a single processor can support up to 16 Threads, and Nehalem architecture Havendale will also be built-in graphics core, not AMD Fusion processor. Added SSE4.2 instruction set and ATA instruction set will also make the system performance is improved.

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